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preliminary 128-mbit (8-mbit x 16) low-power mobl4? sdram cyl008m162ffb cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05448 rev. ** revised may 4, 2004 features ? functionality ? internal 4 bank operation ? standard sdram functionality ? programmable burst lengths: 1, 2, 4, 8, or full page ? compatible with jedec low power sdram standard ? low power features ? low voltage power supply: 1.8v ? temperature compensate d self refresh (tcsr) ? partial array self refresh power-saving mode ? deep sleep mode ? self refresh mode; st andard and low power ? temperature: ?40c to +85c ? 8 mm x 8 mm x 1.0 mm 54-ball 0.8 mm fbga package functional description [1] the cyl008m162ffb is a high- performance cmos dynamic ram (dram) organized as 8m x 16.this device features advanced circuit design to prov ide ultra-low active current and extremely low standby current. this is ideal for providing more battery life tm in portable applications such as wireless handsets. the device is compatible with the jedec standard lp-sdram specifications. logic block diagram cke ras cas we cs clk a0 - a11 ba0 - ba1 control mode enhanced mode refresh counter column decoder logic reg reg sense amp bank 0 memory array 4kx512 bank 0 row addr latch/ decoder row add mux data output reg data output reg bank control logic column address latch write drivers u(l)dqm mask addr reg dq0 - bank 1 bank 2 bank 3 ldqm - udqm (x16) dq15 selection guide device voltage frequency access time t rcd t rp core i/o cl=2 CYL008M162FFBU-1ABAI 1.7 - 1.95v 1.7 - vdd 100mhz 8ns 20ns 20ns note: 1. for best-practice recommendations, please refer to the cypress application note ?system design guidelines? on http://www.cypr ess.com.
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 2 of 46 pin description pin configuration 54 ball fbga(8mm x 8mm x 1.0mm) vddq dq14 dq12 dq9 clk nc udqm nc/ a 6 a 7 dq15 dq13 vddq vss cke a 9 a 11 a 8 3 2 6 5 4 1 d e b a c f g h a 5 j vss v ss v ssq v dd vssq vddq cas ba0 a 0 ldqm dq2 dq0 ras ba1 a 1 dq7 dq1 vdd we cs a 10 v dd 7 8 9 vssq dq11 vssq vddq dq4 dq3 dq5 dq6 dq10 dq8 a12 a 4 a 3 a 2 name type description clk input clock: clk is driven by the system clock. al l sdram input signals are sampled on the positive edge of clk. clk also increments the internal burs t counter and controls the output registers. cke input clock enable: cke activates(high) and deactivates(low) the clk signal. deactivating the clock provides precharge power-down and self refresh operation(all banks idle), active power-down(row active in any bank) or cloc k suspend operation(burst /access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke becomes asynchronous until after exiting the same mode. the input buffers, including clk, are disabled during power-down and self refresh modes, providing low standby power. cke may be tied high. cs input chip select: cs enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. cas , ras , we input command inputs: cas , ras , and we (along with cs ) define the command being entered. l(u)dqm input input/output mask: l(u)dqm is sampled high and is an input ma sk signal for write accesses and an output enable signal for read accesses. input data is masked during a write cycle. the output buffers are placed in a high-z state (two-clock la tency) when during a read cycle. ldqm corre- sponds to dq0 ? dq7, udqm corresponds to dq8?dq15. l(u)dqm are considered same state when referenced as u(l)dqm. ba0, ba1 input bank address input(s): ba0 and ba1 de fine to which bank the active, read, write or precharge command is being applied. these pi ns also provide the op-code during a load mode register command
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 3 of 46 functional description the cypress 128mb sdram is a quad-bank dram that operates at 1.8v and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0 and ba1 select the bank, a0- a11 select the row). the address bits (a0-a8) registered coincident with the read or write command are used to select the starting column lo cation for the burst access.the sdram must be initialized prior to normal operation. the following sections provide detailed information regarding device initialization, register definition,command descriptions and device operation. initialization sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. once power is applied to v dd and v ddq (simultaneously) and the clock is stable (meets the clock specifications in the ac characteristics), the sdram requires a 100s delay prior to issuing any command other than a command inhibit or nop. the command inhibit or nop should be applied atleast once during the 100s delay. after the 100s delay, a precharge command should be applied. all banks must then be precharged, thereby placing the device in the all banks idle st ate. once in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. becaus e the mode register will power up in an unknown state, it should be loaded prior to applying any operational command.refer figure 1. a0 - a11 input address inputs: a0?a11 are sampled during the active command (row- address a0?a11) and read/write command (column-address a0?a8; with a10 defining auto precharge) to select one location out of the memory array in the res pective bank. a10 is sampled during a precharge command to determine if all banks are to be prechar ged (a10 high) or bank selected by ba0, ba1 (a10 low). the address inputs also provide the op- code during a load mode register command. dq[0:15] i/o data input/output: data bus nc - no connect: these pins are not connected to the die v ddq supply dq power: provide isolated power to dqs for improved noise immunity. v ssq supply dq ground: provide isolated ground to dqs for improved noise immunity. v dd supply power supply: voltage dependant on option. v ss supply ground. name type description
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 4 of 46 register definition there are two mode registers which contain settings to achieve low power consumption. the two registers : mode register (mr) and extended mode register (emr) are discussed below. mode register(mr) the mode register is used to define the specific mode of operation of the sdram. this definition includes the selection of a burst length, a burst type , a cas latency, an operating mode and a write burst mode, as shown in table 1.the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power.mode register bits m0-m2 specify the burst length, m3 specifies the type of burst (sequential or interleaved), m4-m6 specify the cas latency, m7 and m8 specify the operating mode, m9 specifies the width burst mode , m10,m11,m12 and m13 should be set to zero.the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initi- ating the subsequent operation. violating either of these requirements will result in unspecified operation. notes: 2. the two auto refresh commands at cycle 4 and cycle 8 may be applied before either load mode register (lmr) command. 3. pre = precharge command, lmr = load mode register command, ar = auto refresh command, act = active command, ra = row address, ba = bank address 4. the load mode register for both mr/emr and 2 auto refresh commands can be in any order; however, all must occur prior to an a ctive command. 5. apply power and start clock, attempt to maintain cke = ?h?, dqm = ?h? 4 other pins are nop condition at the inputs. figure 1. initialize and load mode register [2, 3, 4, 5] high level is necessary u(l)dqm we dq hiz hiz a10/ap ba1 ba0 addr cas ras cs cke clk 0 123 4 56 7 8 9 10 11 12 13 14 15 16 17 18 19 key key raa raa t rp t rc t rc precharge (all bank) auto refresh auto refresh normal mrs extended mrs row active a bank
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 5 of 46 burst length read and write accesses to the sdram are burst oriented.the burst length is programmable, as shown in table 7.the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1,2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is av ailable for the sequential type. the full-page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result.when a read or write command is issued, a block of columns equal to the burst length is effectively select ed.all accesses for that burst take place within this block,me aning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-a8 when the burst length is set to two; by a2-a8 when the burst length is set to four; and by a3-a8 when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached. burst type the burst type can be set to either sequential or interleaved by using the m3 bit in the mode register.the ordering of accesses within a burst is determ ined by the burst length, the burst type and the starting column address, as shown in table 7. table 1. mode register m13- a1 m12- ba0 m11- a11 m10- a10 m9-a9 m8-a8 m7-a7 m6-a6 m5-a5 m4-a4 m3-a3 m2-a2 m1-a1 m0-a0 reserved(set to ?0?) wb op mode cas latency bt burst length table 2. mr - burs t length settings [6, 7, 8, 9, 10, 11 ] m2 m1 m0 burst length m3=0 m3=1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved table 3. mr - burst type setting m3 burst type 0 sequential 1 interleaved table 4. mr - cas latency setting m6 m5 m4 cas latency 0 0 0 reserved 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved table 5. mr - width burst mode setting m9 width burst mode 0 prog. burst length 1 single mode access table 6. mr - operation mode setting m8 m7 m6-m0 operating mode 0 0 defined standard operation - - - all other states reserved note: 6. for a burst length of two, a1-a7 select the block-of-two burst; a0 selects the starting column within the block. 7. for a burst length of four, a2-a7 select the block-of-four burst; a0-a1 select the starting column within the block. 8. for a burst length of eight, a3-a7 select the block-of-eight burst; a0-a2 select the starting column within the block. 9. for a full-page burst, the full row is selected and a0-a7 select the starting column. 10. whenever a boundary of the block is r eached within a given sequence above, the following access wraps within the block. 11. for a burst length of one, a0-a7 select the unique colu mn to be accessed,and mode register bit m3 is ignored.
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 6 of 46 operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts.test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. cas latency the cas latency is the delay, in clock cycles, between the registration of a read command an d the availability of the first piece of output data. the lat ency can be set to one, two, or three clocks. if a read command is registered at clock edge r , and the latency is q clocks, the data will be available by clock edge r + q . the dqs will start driving as a result of the clock edge one cycle earlier ( r + q - 1) , and provided that the relevant access times are met, the data will be valid by clock edge r + q . for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in figure 2. table 8. indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. table 7. burst le ngth definition burst length starting column address order of accesses within a burst type= sequential type = interleaved 2a0 00-10-1 11-01-0 4a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page(y) n=a0-a11(location 0-y) bn,bn+1,bn+2....bn,... not supported
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 7 of 46 figure 2. cas latency nop read command dq t lz t oh t ac cas latency = 1 clk t0 t1 t2 dout nop read command dq t lz t oh t ac cas latency = 2 clk t0 t1 t2 dout nop t3 nop read command dq t lz t oh t ac cas latency = 3 clk t0 t1 t2 dout t3 t4 nop nop
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 8 of 46 extended mode register (emr) the extended mode register co ntrols additional functions such as the temperature com pensated self refresh (tcsr) control, and partial array self refresh (pasr).the extended mode register is programmed via the mode register set command (ba1=1,ba0=0) and reta ins the stored information until it is programmed again or the device loses power. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before befo re initiating any subsequent operation. violating either of these requirements results in unspecified operation. temperature compensated self refresh every cell in the dram requires refreshing due to the capacitor losing its charge over time. the refresh rate is dependent on temperature. at higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be re freshed more often.temperature compensated self refresh (tcs r) allows the controller to program the refresh interval during self refresh mode, according to the case temperature of the device. this allows great power savings during self refresh during most operating temperature ranges. only during extreme tempera- tures would the controller have to select a tcsr level that will guarantee data during self refresh. historically, during self refresh, the refresh rate has been set to accomodate the worst case, or highest temper ature range expected. thus, during ambient temperatures , the power consumed during refresh was unnecessarily high, because the refresh rate was set to accommodate the higher temperatures. setting em4 and em3, allow the dram to accomodate more specific temperature regions during self refresh. there are four temperature settings, which will vary the self refresh current according to the selected temperature. this selectable refresh rate will save power when the dram is operating at normal temperatures. cypress 128mb sdrams will also have a auto temperature self refresh which will automatically adjust the refresh rate based on the temperature without any register update needed. partial array self refresh the partial array self refresh (pasr) feature allows the controller to select the amount of memory that will be refreshed during self refresh. the refresh options are all banks (banks 0, 1, 2, and 3); two banks(banks 0 and 1); and one bank (bank 0). write and read commands occur to any bank selected during standard operation, but only the selected banks in pasr will be refreshed during self refresh. the data in banks 2 and 3 will be lost when the two bank option is used. similarly the data will be lost in banks 1, 2, and 3 when the one bank option is used. slew rate control the slew rate feature allows one to reduce the drive strength of the i/o?s on the device during low frequency operation. this allows systems to re duce the noise asso ciated with the i/o?s switching. table 8. cas latency speed bin allowable operating frequency(mhz) cas latency =1 cas latency =2 cas latency =3 100mhz <=40 <=100 not supported table 9. extended mode register em13- ba1 em12- ba0 em11- a11 em10- a10 em9- a9 em8- a8 em7- a7 em6- a6 m5- a5 em4- a4 em3- a3 em2- a2 em1- a1 em0- a0 1 0 all must be set to ?0? bank up/down slew rate tcsr pcsr table 10.emrs - partial array self refresh selection [12] em7- a7 em2 - a2 em1 - a1 em0 - a0 self refresh coverage x 0 0 0 four banks 0 0 0 1 two banks(bank0,1) 0 0 1 0 one bank(bank0) 1 0 0 1 two banks(bank2,3) 1 0 1 0 one bank(bank2) x011 rfu x100 rfu x101 rfu x110 rfu x111 rfu note: 12. rfu: reserved for future use
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 9 of 46 table 11.emrs - case temperature em4 - a4 em3 - a3 maximum case temperature 1 1 85c 0 0 70c 0 1 45c 1 0 15c table 12.emrs - slew rate control em6 - a6 em5 - a5 slew rate 0 0 100% 0 1 75% 1 0 50% 1 1 30% table 13.commands [13, 14, 15, 16, 17, 18, 19, 20] name(function) cs ras cas we u(l)dqm addr dq command inhibit(nop) h x x x x x x no operation(nop) l h h h x x x active(select bank and activate row) l l h h x bank/ row x read(select bank and column, and start read burst) [20] lhlh l/hbank/ col x write(select bank and column, and start write burst) [20] l h l l l/h bank/ col valid burst terminate l h h l x x active precharge(deactivate row in bank or banks) l l h l x code x auto refresh or self refresh(enter self refresh mode) lllh x x x load mode register l l l l x opcode x write enable/output enable - - - - l - active write inhibit/output high-z - - - - h high z note: 13. cke is high for all commands shown except self refresh. 14. a0-a10 define the op-code written to the mode register. 15. a0-a11 provide row address, and ba0, ba1 determine which bank is made active. 16. a0-a8 provide column address; a10 high enables the auto prec harge feature (nonpersistent), while a10 low disables the auto p recharge feature; ba0, ba1 determine which bank is being read from or written to. 17. a10 low: ba0, ba1 determine the bank being precharged. a10 high: all banks precharged and ba0, ba1 are ?don?t care.? 18. this command is auto refresh if cke is high, self refresh if cke is low. 19. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 20. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clo ck delay). ldqm controls dq0-7, udqm con trols dq8-15, dqm2 controls dq16-23, and dqm3 controls dq24-31.
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 10 of 46 cycle to cycle commands table 14. cke [21, 23, 24] cke n-1 cke n current state command n action n l l power down x maintain power down self refresh x maintain self refresh clock suspend x maintain clock suspend l h power down [25] command inhibit or nop exit power down self refresh [26] command inhibit or nop exit self refresh clock suspend [27] x exit clock suspend h l all banks idle command inhibit or nop power down entry all banks idle auto refr esh self refresh entry reading or writing valid clock suspend entry h h see table 15. notes: 21. cke n is the logic state of cke at clock edge n; cke n-1 was the state of cke at the previous clock edge. 22. current state is the state of the sdram immediatly prior to the clock edge n. 23. command n is the command registered at clock edge n , and action n is a result of command n. 24. all states and sequences not shown are illegal or reserved. 25. exiting power down at clock edge n will put the device in all the banks idle state in time for clock edge n+1(provided the t cks is met) 26. exiting self refresh at clock edge n will put the device in all the banks idle state once t xsr is met. command inhibit or nop commands should be issued on any clock edges occuring during the t xsr period. a minimum of two nop commands must be provided during the t xsr period. 27. after exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n +1.
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 11 of 46 table 15.curent state bank n, command to bank n [28, 29, 30, 31, 32, 33] current state cs ras cas we command(action) any h x x x command inhibit (nop /continue previous operation) l h h h no operation (nop/cont inue previous operation) idle l l h h active (select and activate row) l l l h auto refresh [34] l l l l load mode register [34] l l h l precharge [38] row active l h l h read (select column and start read burst) [37] l h l l write (select column and start write burst) [37] l l h l precharge (deactivate row in bank or banks) [35] read(auto precharge disabled) l h l h read (select column and start new read burst) [37] l h l l write (select column and start write burst) [37] l l h l precharge (truncate read burst, start precharge) [35] l h h l burst terminate [36] write (auto precharge disabled) l h l h read (select column and start read burst) [37] l h l l write (select column and start new write burst) [37] l l h l precharge (truncate write burst, start precharge) [35] l h h l burst terminate [36] notes: 28. this table applies when cken-1 was high and cken is high (see table 14.) and after t xsr has been met (if the previous state was self refresh). 29. this table is bank-specific, except where noted; i.e., the cu rrent state is for a specific bank and the commands shown are t hose allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 30. current state definitions: idle: the bank has been precharged, and t rp has been met.row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in prog ress. read: a read burst has been initiated, with auto precharge di sabled, and has not yet terminated or been terminated. write: a write burst has been init iated, with auto precharge disabled, and has not yet terminate d or been terminated. 31. the following states must not be interrupted by a command issued to the same bank. command inhibit or nop commands, or allow able commands to the other bank should be issued on any clock edge occurring during th ese states. allowable commands to the other bank are determine d by its current state and table 15. and according to table 16.. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when trcd is met. once t rcd is met, the ba nk will be in the row active state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and end s when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registration of a write command with a uto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 32. the following states must not be interrupted by any executable command; command inhibit or nop commands must be applied on e ach positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rc is met. once t rc is met, the sdram will be in the all banks idle state. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. once t mrd is met, the sdram will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when trp is met. once t rp is met, all banks will be in the idle state. 33. all states and sequences not shown are illegal or reserved. 34. not bank-specific; requires that all banks are idle. 35. may or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 36. not bank-specific; burst terminate affects the mo st recent read or write burst, regardless of bank. 37. reads or writes listed in the command (action) column incl ude reads or writes with auto precharge enabled and reads or write s with auto precharge disabled. 38. does not affect the state of the bank and acts as a nop to that bank. table 16.current state bank n,command to bank m [39, 40, 41, 42, 43, 44] current state cs ras cas we command(action) any h x x x command inhibit (nop/c ontinue previous operation) lhhh no operation (nop/continue previous operation) idle x x x x any command otherwise allowed to bank m row activating, active, or precharging llhh active (select and activate row) lhlh read (select column and start read burst) [45] lhll write (select column and start write burst) [45] llhl precharge
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 12 of 46 read(auto precharge disabled) llhh active (select and activate row) lhlh read (select column and start new read burst) [45, 48] lhll write (select column and start write burst) [45, 51, 49] llhl precharge [47] write(auto precharge disabled) llhh active (select and activate row) l h l h read (select column and start read burst) [45, 46, 50] l h l l write (select column and start new write burst) [45, 51] llhl precharge [47] read (with auto precharge) llhl active (select and activate row) l h l h read (select column and start new read burst) [45, 46, 52] l h l l write (select column and start write burst) [45, 46, 54] llhl precharge [47] write(with auto precharge) llhh active (select and activate row) l h l h read (select column and start read burst) [45, 46, 53] lhll write (select column and start new write burst) [45, 46, 55] llhl precharge [47] note: 39. this table applies when cken-1 was high and cken is high and after t xsr has been met (if the previous state was self refresh). 40. this table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allo wable). exceptions are covered in the notes below. 41. current state definitions: idle : the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto prechar ge disabled, and has not yet terminated or been terminated. write: a write burst has been init iated, with auto precharge disabled, and has not yet terminate d or been terminated. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registration of a write command with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 42. auto refresh, self refresh and load mode register commands may only be issued when all banks are idle. 43. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 44. all states and sequences not shown are illegal or reserved. 45. reads or writes to bank m listed in the command (action) column include reads or wr ites with auto precharge enabled and reads or writes with auto precharge disabled. 46. concurrent auto precharge: bank n will initiate the auto precharge command when its burst has been interrupted by bank m ?s burst. 47. burst in bank n continues as initiated. 48. for a read without auto precharge interrupted by a r ead (with or without auto precharge), the read to bank m will interrupt the read on bank n , cas latency later (figure 34.). 49. for a read without auto precharge interrupted by a writ e (with or without auto precharge), the write to bank m will interrupt the read on bank n when registered (figure 35.). u(l)dqm should be used one cloc k prior to the write command to prevent bus contention. 50. for a write without auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered (figure 36.), with the data-out appearing cas latency later. the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 51. for a write without auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the write on bank n when registered (figure 37.). the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 52. for a read with auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the read on bank n , cas latency later. the precharge to bank n will begin when the read to bank m is registered (figure 34.) 53. for a read with auto precharge interrupted by a writ e (with or without auto precharge), the write to bank m will interrupt the read on bank n when registered. u(l)dqm should be used two clocks prio r to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (figure 35.). 54. for a write with auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered, with the data-out appearing cas latency later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m (figure 36.). 55. for a write with auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid write to bank n will be data registered one clock prior to the write to bank m (figure 37.). table 16.current state bank n,command to bank m [39, 40, 41, 42, 43, 44]
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 13 of 46 command operation extended mode register set command (cs , ras, cas, we , ba0 = low, ba1 = high) the lpsdram has an extended mode register that defines low power functions. in this command, a0 through a11 are the data input pins.after power on, the extended mode register set command must be executed to fix low power functions.the extended mode register can be set only when all banks are in idle state.during trsc following this command, the lpsdram can not accept any other commands. mode register set comma nd (load mode register command) (cs , ras, cas , we , ba0, ba1=low) the lpsdram has a mode regist er that defines how the device operates. in this command, a0 through a11 are the data input pins. after power on, the mode register set command must be executed to initialize the device. the mode register can be set only when the banks are in the idle state. during t rsc following this command, the lpsdram cannot accept any other commands. activate command (cs , ras =low, cas , we =high) the lpsdram has four banks, each with 4,096 rows. this command activates the bank selected by ba0 and ba1 and a row address selected by a0 through a11. this row remains active for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. precharge command (cs , ras , we , ba0, ba1=low, cas = high) the precharge command is used to deactivate the active row in a particular bank or the active row in all banks. the bank(s) will be available for a subsequent row access a specified time (t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. this command corresponds to a conventional dram?s ras rising. figure 3. emrs set command figure 4. mr set command clk cke cs ras cas we ba0 ba1 a10 address h clk cke cs ras cas we ba0 ba1 a10 address h figure 5. activate command figure 6. precharge command clk cke cs ras cas we ba0, ba1 a10 address h ro ro clk cke cs ras cas we ba0, ba1 a10 address h ro ro precharge select
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 14 of 46 write command (cs , cas , we =low, ras =high) the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a7 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst. if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the u(l)dqm input logic level appearing coincident with the data. if a given u(l)dqm signal is registered low, the corre- sponding data will be written to memory; if the u(l)dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. read command (cs , cas =low, ras , we =high) read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a8 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst. if auto precharge is not selected, the row will remain open for subsequent accesses. read data appears on the dqs subject to the logic level on the u(l)dqm inputs two clocks earlier. if a given u(l)dqm signal was registered high, the corresponding dqs will be hig h-z two clocks later; if the u(l)dqm signal was registered low, the dqs will provide valid data. auto refresh command (cs , ras , cas =low, we , cke=high) auto refresh is used during normal operation of the sdram. this command is nonpers istent, so it must be issued each time a refresh is required. all active banks must be precharged prior to issuing an auto refresh command. the auto refresh command should not be issued until the minimum t rp has been met after the precharge command. the addressing is generated by the internal refresh controller. the address bits thus are a ?don?t care? during an auto refresh command. the cypress 128mb sdram requires 4,096 auto refresh cycles every 64ms ( t ref ), regardless of width option. providing a distributed auto refresh command every 15.625s will meet the refresh requirement and ensure that each row is refreshed. alternatively, 4,096 auto refresh commands can be issued in a burst at the minimum cycle rate ( t rfc ), once every 64ms before executing auto refres h, all banks must be precharged. after this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. during trc1 period (from refresh command to refresh or activate command), the lpsdram cannot accpet any other command. figure 7. write command clk cke cs ras cas we ba0, ba1 a10 address h figure 8. read command figure 9. auto refresh command clk cke cs ras cas we ba0, ba1 a10 address h col clk cke cs ras cas we ba0, ba1 a10 address h
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 15 of 46 self refresh entry command (cs, ras, cas, cke=low, we =high) the self refresh command can be used to retain data in the sdram( without external clo cking), even if the rest of the system is powered down. th e self refresh command is initiated like an auto refresh command except cke is disabled (low). once the self refresh command is registered, all the inputs to the sdram become ?don?t care? with the exception of cke, which must remain low.once self refresh mode is engaged, the sdram provides its own internal clocking, causing it to perform its own auto refresh cycles. the sdram must remain in self refresh mode for a minimum period equal to t ras and may remain in self refresh mode for an indefinite period beyond that.the procedure for exiting self refresh requires a sequence of commands. first, clk must be st able (meet the clock specifi- cations in the ac characteristics) prior to cke going back high. once cke is high, the sdram must have nop commands issued (a minimum of two clocks) for t xsr because time is required for the completion of any internal refresh in progress. upon exiting the self refresh mode, auto refresh commands must be issued every 15.625s or less as both self refresh and auto refresh utilize the row refresh counter. after the command execution, self refresh operation continues while cke remains low. when cke goes high, the lpsdram exits the self refresh mode. during self refresh mode, refresh interval and refresh operatio n are performed internally, so there is no need for external control. before executing self refresh, all banks must be precharged. power down entry command (cs , cke=low, ras , cas , we =high) after the command execution, power down mode continues while cke remains low. when cke goes high, the lpsdram exits the power down mode. before executing power down, all banks must be precharged. deep power down entry command (cs, cke, we =low, ras , cas =high) after the command execution, deep power down mode continues while cke remains low. when cke goes high, the lpsdram exits the deep power down mode. before executing deep power down, all banks must be precharged. burst stop command(burst terminate ) (cs =we =low, ras , cas =high) this command can stop the cu rrent burst operation.the burst terminate command is used to truncate either fixed-length or full-page bursts. the most recently registered read or write command prior to the burst terminate command will be truncated. figure 10. self refresh entry command clk cke cs ras cas we ba0, ba1 a10 address figure 11. power down entry command figure 12. deep power down entry command clk cke cs ras cas we ba0, ba1 a10 address clk cke cs ras cas we ba0, ba1 a10 address
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 16 of 46 no operation (command inhibit) (cs =low, ras , cas , we =high) the no operation (nop) command is used to perform a nop to an sdram which is selected (cs is low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected.this command is not an execution command. no operations begin or terminate by this command. auto precharge auto precharge is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. auto precharge thus performs the same precharge command , without requiring an explicit command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst. auto precharge does not apply in the full page mode burst. auto precharge is nonpers istent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge time ( t rp ) is completed. figure 13. burst stop command clk cke cs ras cas we ba0, ba1 a10 address figure 14. no operation clk cke cs ras cas we ba0, ba1 a10 address h
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 17 of 46 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied............................................... ?40c to +85c supply voltage to ground potential .... ............. ? 0.4v to 4.6v dc voltage applied to outputs in high-z state [56, 57, 58] .................................... ? 0.4v to 3.3v dc input voltage [56, 57, 58] ................................. ? 0.4v to 3.3v output current into outputs (low)............................. 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current .....................................................> 200 ma dc electrical characteristi cs and operating conditions operating range device range ambient temperature v dd v ddq cyl008m162ffbu industrial ?40c to +85c 1.7v to 1.95v 1.7v to v dd parameter / condition symbol min max units supply voltage vdd(1.8v) 1.7 1.95 v i/o supply voltage vddq(1.8v) 1.7 vdd v input high voltage : logic 1 all inputs [61] vih 0.8*vddq vddq+0.3 v input low voltage : logic 0 all inputs [61] vil -0.3 0.3 v data output high voltage : ioh = -0.1ma voh 0.9*vddq v data output low voltage : iol = 0.1ma vol 0.2 v input leakage current: any input 0v = v in = v dd (all other pins not under test = 0v) iil -5 5 a output leakage current: dqs are disabled; 0v = v out = v dd qioz-55a table 17.ac electrical characteri stics and operating conditions [59, 63] parameter / condition symbol min max units input high voltage: logic 1; all inputs vih 1.4 v input low voltage: logic 0 ; all inputs vil 0.4 v table 18.idd specifications and conditions [59, 61, 64, 65] description parameter description max units operating current (one bank active) idd1 operatin g current: active mode; burst =2 ; read or write ; trc=trc(min); cas latency =3 [64, 65, 67] 60 ma precharge standby current in power down mode idd2p standby current : power down mode : cke=low; all banks idle 250 a precharge standby current in non power down mode idd2n standby current : power down mode : cke=high; all banks idle 10 ma notes: 56. v ih(max) = v cc + 0.5v for pulse durations less than 20ns. 57. v il(min) = -0.5v for pulse durations less than 20ns 58. overshoot and undershoot spec ifications are characterized and are not 100% tested. 59. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (vdd and vddq must be powered up simultaneously. vss and vssq must be at same potential.) the two auto refresh command wake-ups should be rep eated any time the tref refresh requirement is exceeded. 60. all states and sequences not shown are illegal or reserved. 61. in addition to meeting the transition rate specification, t he clock and cke must transit between vih and vil (or between vil and vih) in a monotonic manner. 62. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to voh or vol. the last valid d ata element will meet t oh before going high-z. 63. ac timing and idd tests have vil and vih, with timing referenced to vih/2 = crossover point. if the input transition time is longer than t t (max), then the timing is referenced at vil (max) and vih (min) and no longer at the vih/2 crossover point. 64. idd specifications are tested after the device is properly initialized. 65. idd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs op en. 66. the idd current will increase or decrease proportionally according to the amount of frequency alteration for the test condit ion. 67. address transitions average one transition every two clocks.
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 18 of 46 thermal resistance [70] notes: 68. other input signals are allowed to transition no more than once every two clocks and are otherwise at valid vih or vil level s. 69. cke is high during refresh command period t rfc (min) else cke is low. the idd6 limit is actually a nominal value and does not result in a fail value 70. tested initially and after design or proce ss changes that may affect these parameters. active standby current in power down mode idd3p standby current:active mode; cs =high; cke=low;all banks active after trcd met; no access in progress [66, 68, 69] 2ma active standby current in non power down mode (one bank active) idd3n standby current:active mode; cs =high; cke=high;all banks active after trcd met; no access in progress [67, 69] 20 ma operating current (burst mo de) idd4 operating current : burst mode: continous burst ; read or write : all banks active; vdd = 1.8v cas latency =3 [66, 67, 68, 69] 50 ma refresh current idd5 auto refresh current : t rc =t rc(min ) cas latency=3;cke,cs =high [68, 69] 120 ma self-refresh current idd6(vdd = 1.8v) self refresh current: cke <= 0.2v, 4 banks 150 a self refresh current: cke <= 0.2v, 2 banks 115 a self refresh current: cke <= 0.2v, 1 bank 95 a deep power down current idd7 deep power down 10 a capacitance parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v dd(typ) 4 pf c out output capacitance 6 pf table 18.idd specifications and conditions [59, 61, 64, 65] parameter description test conditions fbga unit ja thermal resistance (junction to ambient) still air, soldered on a 3 x 4.5 inch, two-layer printed circuit board tbd c/w jc thermal resistance (junction to case) tbd c/w ac test loads and waveforms v dd typ v dd output r2 = 14k 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns all input pulses r1= 14k
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 19 of 46 ac characteristics ac characteristics symbol 100mhz units parameter min max clock specifications clock frequency t clk 100 mhz clock period [71] t clks 10 ns clock high time t ckh 3ns clock low time t ckl 3ns synchronous timing specifications input setup time to clock t css 2.0 ns input hold time to clock t csh 1.0 ns clock access time [38] cl=3 t ac (3) ns cl=2 t ac (2) 8 ns cl=1 t ac (1) 22 ns output hold time from clock t coh 2.5 ns data high impedance time [62] cl=3 t hz (3) ns cl=2 t hz (2) 8 ns cl=1 t hz (1) 20 ns active to precharge command t ras 60 120000 ns active to active command period t rc 80 ns active to read or write delay t rcd 20 ns refresh period(4096 rows) t ref 64 ms auto refresh period t rfc 70 ns precharge command period t rp 20 ns active banka to active bankb command t rrd 20 ns transition time [72] t t 0.5 1.2 ns write recovery time [73] t wr 2t ck write recovery time [74] t wr 2t ck exit self refresh to active command [75] t xsr 80 ns read/write command to read/write command [76] t ccd 1t ck cke to clock disable or power-down entry mode [77] t cked 1t ck cke to clock enable or power-down exit setup mode [77] t ped 1t ck u(l)dqm to input data delay [76] t dqd 0t ck u(l)dqm to data mask during writes [76] t dqm 0t ck u(l)dqm to data high-impedance during reads [76] t dqz 2t ck write command to input data delay [76] t dwd 0t ck note: 71. the clock frequency must remain constant (stable clock is defined as a signal cycling withi n timing constraints specified fo r the clock pin) during access or precharge states (read, write, including t wr , and precharge commands). cke may be used to reduce the data rate. 72. ac characteristics assume t t = 1ns. 73. auto precharge mode only. the precharge timing budget (t rp ) begins at 10ns for -100mhz after the first clock delay, after the last write is executed. may not exceed limit set for precharge mode. 74. precharge mode only. 75. clk must be toggled a minimum of two times during this period. 76. required clocks are specified by jedec functionality and are not dependent on any timing parameter. 77. timing actually specified by t cks ; clock(s) specified as a refere nce only at minimum cycle rate. 78. timing actually specified by t wr plus t rp ; clock(s) specified as a refere nce only at minimum cycle rate. 79. timing actually specified by t wr . 80. jedec and pc100 specify three clocks.
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 20 of 46 data-in to active command [78] t dal 5t ck data-in to precharge command [79] t dpl 2t ck last data-in to burst stop command [76] t bdl 1t ck last data-in to new read/write command [76] t cdl 1t ck last data-in to precharge command [79] t rdl 2t ck load mode register command to active or refresh command [80] t mrd 2t ck data-out to high-impedance from precharge command [76] cl=3 t roh (3) t ck cl=2 t roh (2) 2 t ck cl=1 t roh (1) 1 t ck ac characteristics
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 21 of 46 device operation bank/row activation before any read or write commands can be issued to a bank within the sdram, a row in that bank must be ?opened?(activated). this is accomplished via the active command,which selects both the bank and the row to be activated. a read or write command may then be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specification of 20ns with a 100 mhz clock (10ns period) re sults in 2.5 clocks. a subse- quent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the minimum time interval between successive active commands to the same bank is defined by t rc . a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between su ccessive active commands to different banks is defined by t rrd . read operation read bursts are initiated with a read command, as shown in figure 15. the starting column and bank addresses are provided with the read command, and auto precharge is either enabled or disabled for that burst access. for the generic read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address will be available following the cas latency after the read command. each subsequent data-out element will be valid by the next positive clock edge. figure 2. shows general timing for each possible cas latency setting. upon completion of a burst, assuming no other commands have been initiated, the dqs will go high-z. a fullpage burst will continue until terminated. (the burst will wrap around at the end of the page). a continuous flow of data can be maintained by having addtional read burst or single read command. the first data elem ent from the new burst follows either the last element of a comp leted burst or the last desired data element of a longer burst that is being truncated. the new read command should be issued x cycles before the clock
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 22 of 46 edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 16.for cas latencies of one, two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. full-speed random read accesses can be performed to the same bank, as shown in figure 17., or each subsequent read may be performed to a different bank. figure 15. read command read command clk cke high cs ras cas we a0-a8 a9,a11 a10 ba0,1 address enable auto precharge column address disable auto precharge don?t care bank
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 23 of 46 figure 16. consecutive burst reads -transition from burs t of 4 read to a single read for cas latency 1,2,3 nop read t0 t1 t2 t3 t4 nop nop t5 read nop bank bank col n col b dout n dout n+1 dout n+2 dout n+3 dout b dq address command clk cas latency = 1 x= 0 cycles nop read t0 t1 t2 t3 t4 nop nop t5 t6 read nop nop bank bank col n col b dout n dout n+1 dout n+2 dout n+3 dout b cas latency = 2 dq address command clk x=1 cycle
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 24 of 46 figure 16. consecutive burst reads -transition from burs t of 4 read to a single read for cas latency 1,2,3 nop read t0 t1 t2 t3 t4 nop nop t5 t6 t7 read nop nop nop bank bank col n col b dout n dout n+1 dout n+2 dout n+3 dout b cas latency =3 x=2cycles clk command address dq figure 17. random read accesses for cas latency =1,2,3 read read t0 t1 t2 t3 t4 read read nop bank col n dout n dout a dout x dout m dq address command clk cas latency = 1 bank col a bank col x bank col m
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 25 of 46 a read burst can be terminated by a subsequent write command, and data from a fixed length read burst may be immediately followed by data from a write command (subject to bus turnaround limitations). the write burst may be initiated on the clock edge immediately following the last (or last desired) data element from the read burst, provided that i/o contention can be avoided. in a given system design, there may be a possibility that the de vice driving the input data will go low-z before the sdram dqs go high-z. in this case, at least a single-cycle de lay should occur between the last read data and the write command. the u(l)dqm input is used to avoid i/o contention, as shown in figure 18. and figure 19.. the u(l)dqm signal must be asserted (high) at least two clocks prior to the write comm and (u(l)dqm latency is two clocks for output buffers) to su ppress data-out from the read. once the write command is registered, the dqs will go high-z (or remain high-z), regardless of the state of the u(l)dqm signal, provided the u(l)dqm was active on the clock just prior to the writ e command that truncated the read command. the u(l)dqm signal must be de-asserted prior to the write command (u(l )dqm latency is zero clocks for input buffers) to ensure that the written data is not masked. figure 18.shows the case where the clock frequency allows for bus contention to be avoided without adding a nop cycle, and figure 19.shows the case where the additional nop is needed. figure 17. random read accesses for cas latency =1,2,3 read read t0 t1 t2 t3 t4 read read nop bank col n dout n dout a dout x dout m dq address command clk cas latency = 2 bank col a bank col x bank col m t5 nop read read t0 t1 t2 t3 t4 nop bank col n dout n dout a dout x dout m dq address command clk cas latency = 3 bank col a bank col x bank col m t5 nop t6 nop read read
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 26 of 46 figure 18. read to write nop read t0 t1 t2 t3 t4 write bank col n dout n din b dq address command clk cas latency = 3 nop nop t hz t ds u(l)dqm t ck bank colb figure 19. read to write with extra clock cycle nop read t0 t1 t2 t3 t4 nop bank col n dout n din b dq address command clk cas latency = 3 t5 write nop nop bank col b t hz t ds u(l)dqm t ck
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 27 of 46 a fixed-length read burst or a full-page burst may be followed by, or truncated with, a precharge command to the same bank . the precharge command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 21. for each possible cas latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data element(s). the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 22. for each possible cas latency; data element n + 3 is the last desired data element of a longer burst. figure 20. read interrupted by write and u(l)dqm ; cas latency =2 t0 t1 t2 t3 t4 clk t5 t6 t7 t8 read write din n din n+1 din n+2 din n+3 read write din n din n+1 din n+2 din n+3 read write din n din n+1 din n+2 din n+3 dout n cmd u(l)dqm dq cmd u(l)dqm dq cmd u(l)dqm dq read masked by write read masked by u(l)dqm read cas = 2
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 28 of 46 figure 21. read to precharge nop read t0 t1 t2 t3 t4 t5 t6 t7 nop nop bank a col n dout n dout n+1 dout n+2 dout n+3 x=0cycles clk command address dq nop nop bank (a or all) active precharge bank a row t rp cas latency=1 nop read t0 t1 t2 t3 t4 t5 t6 t7 nop nop bank a col n dout n dout n+1 dout n+2 dout n+3 x=1cycle clk command address dq nop nop bank (a or all) active precharge bank a row t rp cas latency = 2
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 29 of 46 write operation figure 21. read to precharge nop read t0 t1 t2 t3 t4 t5 t6 t7 nop nop bank a col n dout n dout n+1 dout n+2 dout n+3 cas latency =3 x=2cycles clk command address dq nop nop bank (a or all) active precharge bank a row t rp figure 22. terminating a read burst nop read t0 t1 t2 t3 t4 t5 t6 t7 nop nop bank col n dout n dout n+1 dout n+2 dout n+3 x=0cycles clk command address dq nop nop nop burst terminate cas latency=1
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 30 of 46 write bursts are initiated with a write command,as shown in figure 23. the starting column and bank addresses are provided with the write comm and, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. during write bursts, the first valid data-in element will be registered coincident with the write command. subsequent data elements will be registered on each successive positive clock edge. upon completion of a fixed-length burst, assuming no other commands have been initiated, the dqs will remain high-z and any additional input data will be ignored (see figure 24.). a fullpage burst will continue until terminated. (wrap around at the end of the page) an example is shown in figure 25. data n + 1 is either the last of a burst of two or the last desired of a longer burst. a write command can be initiated on any clock cycle following a previous write command. full-speed random write accesses within a page can be performed to the same bank, as shown in figure 26. or each subsequent write may be performed to a different bank. figure 22. terminating a read burst nop read t0 t1 t2 t3 t4 t5 t6 t7 nop nop bank col n dout n dout n+1 dout n+2 dout n+3 x=1cycle clk command address dq nop nop nop burst terminate cas latency=2 nop read t0 t1 t2 t3 t4 t5 t6 t7 nop nop bank col n dout n dout n+1 dout n+2 dout n+3 cas latency =3 x=2cycles clk command address dq nop nop nop burst terminate
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 31 of 46 figure 23. write command write command clk cke high cs ras cas we a0-a8 a9,a11 a10 ba0,1 address enable auto precharge column address disable auto precharge don?t care bank
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 32 of 46 data for a fixed-length write burst a full-page write bursmay be followed by, or truncated with, a precharge command to the same bank.the precharge command should be issued t wr after the clock edge at which the last desired input data element is registered. the auto precharge mode requires a t wr of atleast one clock plus time, regardless of frequency. in addition, when truncating a write burst, the u(l)dqm signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the precharge command. an example is shown in figure 28. data n + 1 is either the last of a bur st of two or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until figure 24. write burst - burst length of 2 nop write t0 t1 t2 t3 bank col n din n din n+1 dq address command clk nop nop figure 25. write to write - transition from a burst of 2 to a single write nop write t0 t1 t2 bank col n din n din n+1 dq address command clk write din b bank col b
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 33 of 46 t rp is met. an example is shown in figure 27.. data n + 1 is either the last of a burst of tw o or the last desired of a longer burst. figure 26. random write cycles figure 27. write to read burst of 2 write and read(cas latency =2) write write t0 t1 t2 t3 bank col n din n din a dq address command clk write write bank col a bank col x bank col m din x din m nop write t0 t1 t2 t3 t4 nop bank col n din n din dq address command clk bank col b t5 nop read nop dout b dout b+1 n+1
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 34 of 46 fixed-length or full-page write bursts can be truncated with the burst terminate command. when truncating a write burst, the input data applied coincident with the burst terminate command will be ignored. the last data written (provided that u(l)dqm is low at that time) will be the input data applied one clock previous to the burst terminate command. this is shown in figure 29., where data n is the last desired data element of a longer burst. figure 28. write to precharge figure 29. terminating a write burst nop write t0 t1 t2 t3 t4 nop bank col n din n din dq address command clk bank (a or all) t5 active precharge nop n+1 t6 nop bank a row t wr u(l)dqm t rp t wr @ t ck >= 15ns nop write nop bank col n din n din dq address command nop n+1 active t wr u(l)dqm t rp nop precharge bank (a or all) bank a row t wr @ t ck < 15ns burst write t0 t1 t2 bank col n din n dq address command clk (data) terminate next command (address)
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 35 of 46 precharge the precharge command (see figure 30.) is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time ( t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inpu ts ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. power-down power-down occurs if cke is registered low coincident with a nop or command inhibit when no accesses are in progress. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding cke, for maximum power savings while in standby. the device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. the power-down state is exited by registering a nop or command inhibit and cke high at the desiredclock edge (meeting t cks ). see figure 31. figure 30. precharge command precharge command clk cke high cs cas ras we a0-a9 a10 ba0,1 address column address don?t care bank all banks bank selected
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 36 of 46 clock suspend the clock suspend mode occurs when a column access/ burst is in progress and cke is registered low. in the clock suspend mode, the inter nal clock is deactivated, ?freezing? the synchronous logic. for each posi tive clock edge on which cke is sampled low, the next internal positive clock edge is suspended. any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the dq pins remains driven; and burst- counters are not incremented, as long as the clock is suspended. (see examples in figure 32. and figure 33.) clock suspend mode is exited by registering cke high; the internal clock and related operation will resume on the subsequent positive clock edge. burst read/single write in this mode, all write commands result in the access of a single column location (burst of one), regardless of the programmed burst length. the burst read/single write mode is entered by programming the write burst mode bit (m9) in the figure 31. power down clk command input buffers gated off all banks idle nop nop active t rcd t ras t rc enter power down mode exit power down mode t cks >=t cks cke
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 37 of 46 mode register to a logic 1. read commands access columns according to the programmed burst length and sequence. figure 32. clock suspend during write burst write nop t0 t1 t2 t3 t4 nop din din address command clk t5 nop n cke clk internal din n+1 din n+2 bank col n
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 38 of 46 concurrent auto precharge if an access command with auto precharge is being execeuted ; an access command (either a read or write ) is not allowed by sdram?s. if this feature is allowed then the sdram supports concurrent auto precharge. cypress sdrams support concurrent auto precharge. four cases where concurrent auto precharge occurs are defined below. read with auto precharge 1. interrupted by a read(with or without auto precharge): a read to bank m will interrupt a read on bank n,cas latency later. the precharge to bank n will begin when the read to bank m is registered. (figure 34.) 2. interrupted by a write(with or without auto precharge): a write to bank m will interrupt a read on bank n when regis- tered. u(l)dqm should be used two clocks prior to the write command to prevent bus content ion. the precharge to bank n will begin when the write to bank m is registered. (figure 35.) write with auto precharge 3. interrupted by a read(with or without auto precharge): a read to bank m will interrupt a write on bank n when regis- tered , with the data-out appearing cas latency later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m.(figure 36.) 4. interrupted by a write ( wit h or without auto precharge): a write to bank m will interrupt a write on bank n when regis- tered. the precharge to bank n will begin after t wr is met ,where t wr begins when the write to bank m is registered. the latest valid data write to bank n will be data registered one clock prior to a write to bank m.( figure 37.) figure 33. clock suspend during read burst - burst of 4 (cas latency =2) nop read t0 t1 t2 t3 t4 nop dq address command clk t5 nop cke clk internal dout n dout n+2 t6 nop dout n+3 nop bank col n dout n+1
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 39 of 46 figure 34. read with auto precharge interrupted by a read(cas latency =3) nop t0 t1 t2 t3 t4 nop dq address command clk t5 nop dout a dout d t6 nop dout d+1 nop read-ap bank n read-ap bank m t7 nop bank n col a bank m col d dout a+1 cas latency =3(bank n) cas latency=3(bank m) page active read with a burst of 4 interrupt burst precharge idle bank n page active read with burst of 4 precharge bank m internal states t rp bank n t rp - bank m figure 35. read with auto precharge interrupted by a write(read cas latency =3) t0 t1 t2 t3 t4 dq address command clk t5 nop dout a din d+1 t6 nop din d+2 nop t7 nop din d read with a burst of 4 bank n page active write with burst of 4 write-back bank m internal states t rp bank n t rp - bank m read-ap bank n nop nop write-ap bank m page active interupt burst,precharge idle bank n col a bank m col d u(l)dqm din d+3 cas latency =3 (bank n)
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 40 of 46 figure 36. write with auto precharge interrupted by a read(cas latency =3) t0 t1 t2 t3 t4 dq address command clk t5 nop din a t6 nop dout d nop t7 nop din a+1 write with a burst of 4 bank n page active read with burst of 4 write-back bank m internal states t wr bank n t rp - bank m nop write - ap read - ap page active interupt burst,write-back bank m col d dout d+1 bank n bank m nop precharge t rp - bank n bank n col a cas latency =3(bank m) figure 37. write with auto precharge interrupted by a write t0 t1 t2 t3 t4 dq address command clk t5 nop din a t6 nop din d nop t7 nop din a+1 write with a burst of 4 bank n page active write-back bank m internal states t wr - bank n t rp - bank n nop write - ap page active interupt burst,write-back bank m col d din d+3 bank n nop write - ap t wr - bank m bank n col a bank m precharge write with a burst of 4 din d din a+2 din d+1 d+2
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 41 of 46 read/write operation. note: 81. minimum row cycle times is required to complete internal dram operation. 82. row precharge can interrupt burst on any cycle.[cas latency -1] number of valid output data is available after row precharge . last valid output will be hi-z(t shz ) after the clock. 83. access time from row active command. tcc *(t rcd + cas latency - 1) + t sac 84. out put will be hi-z after the end of burst. (1,2,3,8 & full page bit burst) figure 38. read & write cycle at same bank @burst length=4, tdpl=1clk (100mhz) 0 1 2 3 45 678 910 1112 1314 151617 1819 clock cke cs ras cas addr ba0 ba1 a10/ap dq /we u(l)dqm row active (a - bank) precharge read row active (a - bank) high t rc t rcd raa ca ra cb t rac qa0 qa1 qa2 qa3 t coh t shz t sac db0 db1 db2 db3 t dpl cl = 2 cl = 3 t rac qa0 qa1 qa2 qa3 t oh t shz t sac db0 db1 db2 db3 t dpl (a - bank) (a - bank) precharge (a - bank) write (a - bank) ra rb don?t care *note *note *note 83 *note 83 *note 84 *note
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 42 of 46 figure 39. read & write cycle at same bank @burst length=4, tdpl=2clk (100mhz) 0 1 2 3 45 678 910 1112 1314 151617 1819 clock cke cs ras cas addr ba0 ba1 a10/ap dq we u(l)dqm row active (a - bank) precharge read row active (a - bank) high t rc t rcd raa ca ra cb t rac qa0 qa1 qa2 qa3 t oh t shz t sac db0 db1 db2 db3 t dpl cl = 2 cl = 3 t rac qa0 qa1 qa2 qa3 t oh t shz t sac db0 db1 db2 db3 t dpl (a - bank) (a - bank) precharge (a - bank) write (a - bank) ra rb don?t care *note *note 82 *note 85 *note 84 *note 85 *note 84
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 43 of 46 deep power down the lpsdram has an extremely low power mode called deep power down. in this mode the device does not refresh internal data and data integr ity is not guaranteed. figure 41.shows the entry to this mode. exit from this mode is similar to a power up sequence as shown in figure 1. notes: 85. row precharge will interrupt writing. last dat a input, tdpl before row precharge, will be written. figure 40. page read & write cycle at same bank @ burst length=4, tdpl=2clk 0 1 2 3 45 678 910 1112 1314 151617 1819 clock cke cs ras cas addr ba0 ba1 a10/ap dq we u(l)dqm row active (b - bank) precharge read row active (a - bank) high raa caa cl = 2 cl = 3 (a - bank) (a - bank) precharge (c - bank) qaa0 qaa1 qaa2 qbb0 qbb1 qbb2 qcc0 qcc1 qcc2 qdd0 qdd1 qdd2 rbb rcc rdd cbb ccc cdd raa rbb rcc rdd qaa0 qaa1 qaa2 qbb0 qbb1 qbb2 qcc0 qcc1 qcc2 qdd0 qdd1 qdd2 read (b - bank) read (c - bank) read (d - bank) row active (c - bank) row active (d - bank) precharge (b - bank) precharge (d - bank) *note
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 44 of 46 ordering information figure 41. deep power down entry we add a10 ba1 cas ras cs cke clk 0 123 4 56 7 8 9 10 11 12 13 14 15 16 17 18 ba0 dqm dq precharge all banks command deep power down entry speed (mhz) ordering code package name package type operating range 100mhz CYL008M162FFBU-1ABAI bv54b 54 vfbga (8 x 8 x 1.0 mm) industrial
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 45 of 46 mobl4 is a part of the low-power sram family and continues the cypress tradition of providing low-power solutions to the wirele ss market. mobl is a registered trademark, and mobl4 and more batte ry life are trademarks, of cy press semiconductor corporation. all product and company names mentioned in this docume nt are the trademarks of their respective holders. package diagrams a 1 a1 corner 0.80 +0.03 ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.320.05 1.00 max c seating plane 0.40 max. 0.25 c 0.15 c a1 corner top view bottom view 2 3 4 6.40 6.40 b c d e f g h 65 46 5 23 1 8.000.10 8.000.10 a 8.000.10 8.000.10 b 3.20 3.20 0.26 max. 0.80 987 79 8 j j h g f e d c b a ?0.45 (54x) -0.07 reference jedec mo-207 54 vfbga (8 x 8 x 1.0 mm)?045 mm ball dia. bv54b 51-85197-**
preliminary cyl008m162ffb document #: 38-05448 rev. ** page 46 of 46 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. document history page document title : 128-mbit (8-mbi t x 16) low-power mobl4? sdram document # 38-05448 rev. ecn no. issue date orig. of change description of change ** 223921 see ecn hrt new data sheet

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